Because the devices manufactured on SOI wafers possess the advantages of anti-radiation, latch-up immunity and high speed and moreover the development of the SOI wafers has obtained a great progress in recent years, the applications of the SOI waters in VLSI are more and more important.
In spite the natural electrical isolation between a device and its underneath substrate is provided by SOI wafers, the isolation between devices in the lateral direction, however, still has some problems unsolved.
Please refer to FIG. 1 which is an elevational cross-section view schematically showing an SOI wafer, on which a MOSFET device is constructed with a conventional isolation method. The layers shown in FIG. 1 include a silicon substrate 1, a buried dielectric layer 2, a silicon-film island region 3, a gate oxide layer 4 and a side-wall oxide layer 41 located between the silicon-film island region 3 and the polysilicon gate 5.
During the operation of such SOI MOSFET shown in FIG. 1, the comer 32 of the silicon-film receives the electric lines from both top gate and side-wall gate. Therefore, the threshold voltage of the parasitic corner transistor is smaller than that of the main transistor at top surface. The side wall 31 of the silicon island due to island definition etching not only concentrates thereon a higher density of surface charge, which may render the threshold voltage of the parasitic side-wall transistor lower, but also has a defective and damaged surface. As a result, potential leakage paths between the drain and the source are formed at the side wall 31 and the comer 32. An undesired high subthreshold current may be conducted between source and drain through this leakage path, when the main transistor is in "off" state, i.e. when the gate to source voltage is smaller than the top transistor threshold voltage.